You have got this empty project , now you need to add source file to it , right click on target name in the hierarchy window on the left , then click new source
to add new source you got many options , but you need to add only verilog file for now. select verilog module , specify the name , the name here need a little attention , the verilog file name and module name is always going to be same , the wizard will automatically add the new module with the same name in to newly created verilog file , do not change the name it verilog source ever, if wanted to change module name then need to change the file name also.
if you want you can speicfy all the ports you module going to have , as it will automatically create verilog file for you , but i like it to directly enter in the source so enter nothing and just hit next ,
you have got the editor type your source here , the module source it the real stuff, it actually tells what is need to be done and when , it define all the intelligence the module has.
