Hardware .
For this particular experiment I am using my WireFrame FPGA Bord. almost any FPGA can be used for this experiment there no such dependency on any specific part, you are free to use any vendor’s part ,the verilog code going to be same though the process of implementing the module, working environment and procedure or programming the part is going to be a little different. my board has Xilinx XC3S250E FGPA , the FPGA it self has many I/O line but most of them are used for on board RAM , only 30 I/O line (out which few are only input) are available for use.
we are going to use only 5 I/O line , 3 for counter output and 1 for counter reset input. one more I/O line we need is Clock input but as we have the 25Mhz crystal oscillator on board , it is already connected to I/O pin number 89.
you can chose any I/O line with required capability to use as counter output and reset input , we have made the connection are as following.
port rst at location = P88
port clk at location = P89;
port count bit 2 (MSB) at location = P79;
port count bit 1 Location= P78;
port count bit 0 (LSB at location = P68;
you need to apply requisite power , and connect led to the out pins if you like.
why only 3 bits, 23 ,24,25 are mapped to hardware? it is just a simple little test , we can easily verify the weather the counter is counting with 2-3 output pins , i don’t want to mess with many many connection in the hardware, 3 outputs are enough to see if it actually working. and i am very lazy to connect unnecessary hardware to the FPGA.
And i connected 23 , 24 ,25 bits bit of the counter with a simple logic , we have 25Mhz clock input and we wanted to see the binary counter with our counting on led directly with our naked eyes, if you see the a binary counter’s behaviour ,next higher significance bit toggle only after the former lesser significance bit toggle twice (because binary number are base of 2) . this can also be said like on every next higher significance bit output the input is divided by 2.
as we have 25Mhz input , on bit 0 of counter output we will get 12.5 Mhz and on bit 1 we will get 6.26Mhz and so on, i can see signal changing this fast with my eyes .so i need to divide this further in the range of less than 10Hz or so.
at bit 23 , which is 24th bit in output starting from bit 0. you got the input clock 25Mhz divided by 2^24 ,output at bit 23 will be 25Mhz/(2^24) = 2.98 Hz , at 24 bit it wil be 0.745 Hz and at bit 25 it will be 0.3275 Hz , we can easily see such a low frequency with led.
Making Port Mapping with ucf file
every single signal in verilog treated as NET ,
so the syntax says NET rst is connected to Location Pin Number 88 and so on .
NET “rst” LOC = P88;
NET “clk” LOC = P89;
NET “count[24]” LOC = P78;
NET “count[25]” LOC = P79;
NET “count[23]” LOC = P68;
as count is an Output , and in verilog you have to define the IO Standard of ever output , as FPGA are capable of many different type of IO Standards like 2.5V CMOS or 3.3V CMOS etc. you need to tell here what exactly you want.
NET “count[0]” IOSTANDARD = LVCMOS33;
NET “count[19]” IOSTANDARD = LVCMOS33;
NET “count[20]” IOSTANDARD = LVCMOS33;
