Source Code and Design file
all the source code is available in the github repo WireFrame-FPGA/VerilogHDL-Modules/counter_wireframe,
https://github.com/circuitvalley/WireFrame-FPGA
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Final testing
you can take a look at the video of the test with 3 LEDs, please note you need to connect at pullup ~10K at reset line I/O30 P88, it is under the board in this video.
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