[tps_header][/tps_header]
This article is goint be very very basic , like how to create xilinx ISE project and write a little binary counter in verilogHDL , how to wireup the module’s port to I/O line of the FPGA . and finally implement the module , we will also simmulate the design with the help of verilog Test bench in model sim software. After getting happy simulation result we will generate programming file(.bit file) and flashing the bit file directly into FPGA with help of a low cost JTAG cable.
Counter Module
we have to implement a module as show in the diagram.
there are only Two source file you need to write to make you own counter module
counter.v file , VerilogHDL source file which define the logic behind the module
we will use Behavioural modelling technique,in which you just
have to specify what behaviour you want your module to do .
the tool automatically implements the hardware for job
counter.ucf file, this fill will have mapping information about the FPGA
Hardware pins and the Module ports
that is all you don’t need to supply anythig else everything else is done by the tool.
so lets start with the port definition
verilog module port are define defined , like parameter in a c function
for us it will like , we don’t need to give exact direction and size here we and put this later on in the module description it self.
| module counter( | |
| rst, //Reset input | |
| clk, //clock output | |
| count // count output | |
| ); |
| parameter size = 32; | ||
| input rst; // reset the counter | ||
| input clk; // connected to WireFrame on board 25Mhz crystal. | ||
| output [size–1:0] count; //count is bus with width of size ,which is defined as parameter with value 32 |
reg [size–1:0] count; //declared count as a register
| always @ (posedge clk) // this always block , runs always on when a positive edge comes on the clock (clk) input | |
| begin | |
| if (!rst) // This causes reset counter | |
| count = 0; | |
| else | |
| count = count + 1’b1; // if reset is not low then keep incrementing count value at every positive clock edge | |
| end | |
endmodule //module ends here
that is all there is nothing else to it. logic part is done now we need to wire these port to the I/O line of FPGA. for that we need to create a .ucf file.
