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VXO — based PLL Frequency Synthesizer for 7 MHz

VXO — based PLL Frequency Synthesizer for 7 MHz


In EMRFD, 4.10, Wes provides the schema for a versatile VXO – extending frequency synthesizer. Although, I referred him to Wes for help, a reader asked me some questions and I ended up designing some pieces for him. In order to test some of my ideas, I made a VXO – based synthesizer that tuned from 6.99 to 7.103 MHz using only parts I had in stock.

For those interested, here’s some project schematics, notes and images:

Above — Block out of the synthesizer.


Above — Schematic of the reference oscillator. I’ve discussed this circuit before here

Above — Output of the 1 MHz CMOS clock applied as the reference oscillator. Initially, I planned to divide a 2 MHz crystal oscillator in half with a flip-flop circuit, but remembered that someone sent me some high-grade 1 MHz clocks a few years ago.

Above — A test of the entire circuit with the 4 switches configured 0001 for divide by 3.


To make a VXO to mix with a ~7 MHz VCO, you’ll need a crystal that is higher in frequency than the highest frequency you want to synthesize. Some rummaging revealed a bag of 21.4773 MHz crystals that I could divide by 3 to garner 7.159 MHz.

To afford a reasonable delta F, three were placed in the super VXO fashion and I applied the smallest amount of series inductance that would ensure a reasonable delta F with solid frequency stability.

Above — The schematic of my VXO. Through experiments I determined that 3 crystals and the inductance shown gave a stable ~30 KHz swing in frequency when divided by 3. A BD139 with low flicker noise gets buffered, digitized and then buffered again by a single inverter crafted by an AND gate.

The simple divide by 3 circuit lacks a 50% duty cycle, but worked OK. A low cutoff frequency low-pass filter serves to clean up the waveform, plus attenuate the output signal so that it is somewhere between 200 and 300 mV peak to peak to chop the NE612 mixer without excessive distortion in the mixer output.

Dividing by 3 drops the raw VXO range by 1/3, the phase noise by ~ 9.5 dB and also reduces frequency drift even further.

Above — A DSO trace of the Pin 9 digital output @ 7.14 MHz


Above — The low-pass filtered and attenuated output. Now at a 50% duty cycle.

Above — The VXO breadboard on my lawn. The yellow RCA coupler = the 12.3 volts DC input.


Above — The entire offset mixer stage.

Above — The output of offset mixer stage just at the collector of the final transistor used to digitize and feed the Phase Frequency detector [ ~ 100 KHz offset ]. I first tested it with a 7 MHz bench signal generator offset from the VXO by ~143 KHz to 58 KHz.


Above — VCO breadboard. I wanted to keep this circuit for later experiments, so I stuck it in a RF – tight, die-cast box with 2 SMA connectors for the RF outputs, a BNC connector for the frequency counter, plus an RCA panel-mount for the DC input. Finally, I placed a feed through capacitor for PLL control.

Above — VCO schematic. I plied the low flicker noise BC337 in the ripple filter and oscillator slots. Since I can’t go much above 7.1 KHz with my VXO crystal frequency, I kept it narrow band plus well filtered the DC voltage lines to lower phase noise as possible. Typical VFO construction techniques for temperature and mechanical stability were plied. For example, NP0/COG tank capacitors, and a well anchored, single-sided, copper clad board.

We see great emphasis on making “pretty circuits” in the maker community. While charming, even prettier are those “unseen” RF circuits enclosed in RF-tight boxes with proper DC filtering to keep RF where it is supposed to be.

Above — VFO buffer amps. I designed this buffer circuity for high isolation while running just enough current to avoid degrading signal fidelity. In a VXO – based synthesizer, a frequency counter is essential, so a dedicated buffer makes sense.

Above — the raw output leaving the emitter follower just before it gets split into the 2 JFET amps.


Above — The main, low-pass filtered VCO output and the unfiltered output that drives the RF port of the offset mixer.


Above — The PFD plus loop filters. Making a PLL means compromising to get the best overall design. We want to suppress the reference spurs or side bands as much as possible while keeping phase noise low — and — the loop stable. I tweaked my loop filter, plus the phase and VCO filters to keep this loop from oscillating during my tests. To me, this provides enjoyable fun and bench learning.

PFD Polarity

When you first connect the PLL board, you may find that your VCO phase locks on the wrong side of the offset: for example at ~7.3 MHz. The cure for this came from Wes, W7ZOI — ” swap the clock inputs for your D flip flops”. PFDs have polarity!

Above — Spectrum analysis to examine reference side band suppression with a 30 Hertz RBW. In this case, the R = divide by 7 for  ~143 KHz.  I set a marker on the worse of the 2 reference spurs: -83.75 dB down from the main 6.99 MHz tone.

Reference Frequency Divider Table and Discussion

Above — The divider table. Recall that the reference oscillator has 4 switches which you set high or low ( 1 or 0 ). This synthesizer offers 10 switch settings (bands) where the PLL will lock. Since the VXO swings up to ~30 KHz, a large number of frequencies may be generated between the high and low frequency shown for each of the 10 switched bands.

VXO’s do not tune linearly, however, its still possible to get resolution down to the hundred or 10s of hertz for most bands. For example, I’m able to tune 7.000000 MHz or 7.0600 MHz.

Since the bands overlap, a frequency counter helps immensely. A small frequency counter maybe purchased or built for a receiver project.

Further, I show the measured tuning voltage for each of the 10 bands [ high and low ]. For phase noise, it’s important to keep this value above 2 VDC at the lowest frequency. Since this is only a narrow band VCO, I chose 4 VDC as my minimum varactor tuning voltage.


[1] Set the reference divider set to divide by 7 and fully mesh the air variable cap on the VXO
[2] Connect a 10X ‘scope probe to the output of the offset mixer.
[3] Let the system phase lock. You’ll see it lock at ~143 KHz
[4] View a voltmeter clipped onto the output of the VCO filter.
[5] Once the system phase locks,  gently spread or squish the VCO toroid coils plus tweak the trimmer so that at the lowest frequency [ 6.99 MHz ] the varactors are getting about 4 VDC (or whatever you want).
[6] Test the switches to look for instability and so you don’t go above 10.6 VDC or so at the highest frequency.

Video 1   Showing frequency stability in a HP counter with ovenized crystal reference

Video 2    Inside the loop

Clipping a 10X ‘scope probe to the output of the offset mixer helps you peer inside the loop, look for phase lock, instability,  how fast your loop responds and much more.

The VXO extension concept may be taken into UHF — nested loops, multipliers and the like. Not many people make synthesizers anymore since its easier to use 1 chip plus an I/O device. Still, you can learn a lot and have fun with a bit of old school discrete electronics from time-to-time.


 Digital Dividers + / – Modulus Control

For this project, I spent 2 weeks studying digitally dividing by 3 plus other numbers using Johnson counters and also with computer code.

If you have 14.XXX MHz crystal, divide by 2  is easy to accomplish by 2 flip-flops and this gives you a 50% duty cycle.

Its possible to apply modulus control (MC) in varies schemes to make pre-scalers and so forth.
The samples that follow just run CMOS ICs but gives you the general idea how engineers divide F with high speed logic such as ECL.


Above —  Divide by 2 or 3.


Above —  Divide by 4/5 counter where MC = HIGH so divide by 5

Finally, a good primer for how to divide with computer code: Click.