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The ARM1 processor’s flags, reverse engineered

The ARM1 processor’s flags, reverse engineered

The circuit to store a flag

This section discusses how the negative (N) flag works.
The other flags operate similarly, but with some differences, and will be discussed in later section.
The schematic below shows the circuit for the negative flag;
this flag is at the bottom of the chip layout above.
If you’re expecting flags to be stored in a flip flop or regular latch,
this circuit may seem unusual.
Flags are stored in a dynamic two-phase flip-flop, which uses stray capacitance to
store the value.
The basic idea is the value goes around in a loop, amplified by the four inverters, and controlled by the clock.
The trapezoids in the schematic are pass-transistor multiplexers[3]
Each multiplexer has two inputs and two control lines; if a control line is active, the corresponding input is connected to the output.

Circuit for one flag (N) in the ARM1. The flag is stored in a two-phase dynamic latch. Two multiplexers (trapezoids) select values to store in the flag.

Circuit for one flag (N) in the ARM1. The flag is stored in a two-phase dynamic latch. Two multiplexers (trapezoids) select values to store in the flag.

The storage loop consists of two parts, alternately connected by the clock.
During the first clock phase, Φ1, the multiplexer on the left is inactivated by its inputs and generates no output. It holds its previous output due to stray capacitance at the point marked “hold during Φ1”. The signal goes around the loop, through the Φ1 transistor on the right, and up to the input of the multiplexer.
When the clock switches to Φ2, the multiplexer becomes active again, and the transistor on the right switches off. Now, the signal to the left of the transistor is held by the capacitance and flows around the loop until it reaches the transistor and is blocked. Thus, during each clock phase, half the loop is stable and half the loop can be updated. Alternatively, you can consider each half a simple latch and the two parts form a master-slave latch.



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The main use of the condition flags is
for conditional instructions — executing an instruction if the condition is satisfied.
The flag out wire in the diagram goes to the conditional instruction logic
which controls execution by checking the flag values to determine if the condition is satisfied
(details),

The typical way the condition flags are updated is after performing a data processing operation, e.g. ADD. If the result is negative, the N flag is set; otherwise, the N flag is cleared.
The multiplexer on the right allows the new flag value from the ALU to be selected instead of the recirculating value. This happens if the aluflag control signal is activated.

The second way to update the condition flags is to write to them directly, for instance to restore the flag values after handling an interrupt.
The flags can be written from the ALU data bus (which is different from the flag value from the ALU described earlier). The multiplexer on the left selects this value instead of the recirculating value if the writeflags signal is active.

The condition flags can be read directly, for instance to save the flag values while handling an interrupt. The transistors on the left allow the flags to be written to the B bus when the psr_oen (PSR output enable) control signal is activated.

The diagram below zooms in on the chip layout of the N flag, which can be compared with the schematic.
The wire that recirculates the flag from the right to the left is indicated.
You can see the transistors that form the inverters and multiplexers. Details on how the red NMOS transistors and blue PMOS transistors work together to form inverters are
here.

The circuitry for one flag (N/negative) in the ARM1 processor.

The circuitry for one flag (N/negative) in the ARM1 processor.

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