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The ARM1 processor’s flags, reverse engineered

The ARM1 processor’s flags, reverse engineered

One interesting thing about the M0 and M1 flags is they are connected directly to the M0 and M1 output pin driver circuits, shown below. This circuit supports tri-state output (electrically disconnecting the output so the signal can be controlled externally) as well as input, even though neither of these features is used for the M0 and M1 pins. The reason is the same pin driver circuit is reused for all the ARM1 output pins regardless of whether or not they need these features. This is another example of how the ARM1 was designed for simplicity, rather than optimizing the design.
Note that large transistors to provide the output current to the pin.

Driver for the M0 mode output pin. Much of the circuit is unused, since the same circuit is used for most I/O pins.

Driver for the M0 mode output pin. Much of the circuit is unused, since the same circuit is used for most I/O pins.

Register control

One feature of the ARM1 processor is has multiple register banks, controlled by the mode flags.
While there are 16 logical registers (R0 through R15), there are 25 physical registers. Each of the four modes has its own R13 and R14. The fast interrupt mode also has its own
R10, R11 and R12.[6]
These register banks improve performance by allowing interrupt handlers to use registers without needing to save the user registers.


The flag circuitry generates the signals that select the register bank. These signals go to the registers control circuitry next to the registers, where they are used to select particular registers
The bank select signals are

bs0: general (non-fast-interrupt) registers.

bs1: fast interrupt registers.

bs2: regular interrupt registers.

bs3: supervisor registers.

bs4: user registers.

These (low-active) signals are generated from the M0 and M1 flags, which specify the mode.
Registers R10-R12 use bs0 and bs1 to select the appropriate bank for fast interrupts or otherwise. Registers R13 and R14 use bs1, bs2, bs3 and bs4 to select between the four register banks.

One complication is for LDM/STM instruction, the S flag causes the user register bank to be used instead of the expected register bank.
(This is a feature so interrupt handlers can access user registers if desired.)
This happens if the pla2_psrw line is high, indicating a LDM/STM instruction; instruction register bit 22 is high (the S bit for LDM/STM); and pla2_nben is low, indicating bus B enabled.
The pla2_psrw and pla2_nben signals are generated by the instruction decode circuits

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