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Reverse engineering the popular 555 timer chip (CMOS version)

Reverse engineering the popular 555 timer chip (CMOS version)


At first, a chip die photo seems too complex to understand.
But a careful look at the die of the LMC555 CMOS timer chip reveals the components that make up the circuit. One can pick out the PMOS and NMOS transistors, see how they are combined into circuits, and understand how the chip operates.
Because the CMOS chip has a layer of polysilicon that isn’t present in the classic bipolar 555 chip, it takes more effort to understand the CMOS chip.
But fundamentally, both chips use similar analog functional blocks: the current mirror and the differential pair.

If you’ve found this look at the CMOS version of the 555 chip interesting, you should also look at my
teardown of the classic 555 chip.

Thanks to Zeptobars for the die photo of the CMOS chip.


Notes and references

The book Designing Analog Chips written by the 555’s inventor Hans Camenzind is really interesting, and I recommend it if you want to know how analog chips work.
Chapter 11 has an extensive discussion of the 555’s history and operation. Page 11-3 claims the 555 has been the best-selling IC every year, although I don’t know if that is still true — microcontrollers have replaced timers in many circuits.
The free PDF is here


The structure of a MOSFET transistor explains several things about it.
The transistor is called a “field-effect transistor” (FET) because it
is controlled by the electric field on the gate.
Because the gate is separated by an insulating oxide layer, there is essentially no current flow through the gate. This is why CMOS circuits have such low power consumption.
The thin oxide layer, however, can easily be damaged or destroyed by static electricity, which is why MOS integrated circuits are sensitive to static electricity.


For simplicity, the cross-section diagram doesn’t show the highly-doped P region (pink) that provides a connection to the underlying P body silicon, keeping it at the right voltage.
(A via between the metal layer and pink silicon region is visible at the top of the diagram.)
MOS transistors typically connect the source and body silicon together;
the source and drain are otherwise structurally the same.
I should also mention that the cross-section is simplified;
in a real chip, the layers are more irregular.

MOS transistors originally used metal for the gate so they were named MOS after the three layers: Metal, Oxide, and Semiconductor (silicon).
Although polysilicon gates replaced metal gates since the 1970s,
the name remains MOS even though POS would be more accurate.
Federico Faggin (a developer of the 4004 and Z-80 processors) explains how
silicon gate technology revolutionized chips

The structure of the transistor controls how much current flows through it.
In particular, the current is proportional to the ratio of the gate’s width
and length (W/L). It’s straightforward to see that doubling the width of the gate is similar to putting two transistors side-by-side in parallel, allowing twice the current.
Doubling the length of the gate (so the current needs to travel twice as far through the gate) cuts the current in half due to physics reasons.


Two NMOS transistors in the LMC555 chip's flip flop. The left transistor is typical. The right transistor is a weak transistor with current flowing top to bottom.

Two NMOS transistors in the LMC555 chip’s flip flop. The left transistor is typical. The right transistor is a weak transistor with current flowing top to bottom.

In the CMOS 555 chip, transistors have a wide variety of W/L ratios, especially to control the currents in different branches of the current mirrors.
Some of the weak transistors are hard to spot, such as the above weak transistor from the flip flop. The transistor on the left has a W/L ratio of about 7.
The transistor on the right looks almost identical but careful examination shows it is actually rotated 90 degrees with the source and drain arranged vertically rather than horizontally.
The W/L ratio of the transistor on the right is only about 0.17, making the transistor about 40 times weaker than the one one the left.
In other words, the transistor on the left has a wide, short gate while the transistor on the right has a narrow, long gate.

For more information about current mirrors, check wikipedia, any analog IC book, or chapter 3 of
Designing Analog Chips.

Differential pairs are also called long-tailed pairs.
According to
Analysis and Design of Analog Integrated Circuits
the differential pair is “perhaps the most widely used two-transistor subcircuits in monolithic
analog circuits.” (p214)
For more information about differential pairs, see wikipedia, any analog IC book, or chapter 4 of
Designing Analog Chips.


Because CMOS only uses power when circuits change state, power consumption is roughly proportional to frequency. This is the main limitation for CPU clock frequency: the chip will overheat if it is clocked too fast.


Note that the three resistors for the voltage divider are parallel and next to each other.
This helps ensure they have the same resistance even if there are electrical variations across the silicon.


If you want a 555 timer that provides a long delay up to days,
the CSS555 is an unusual option.
This chip is pin-compatible with the 555, but internally it includes
a programmable counter that can divide the output up to 1 million.
The chip contains a one-byte EEPROM to hold the configuration and is programmed
serially via the trigger and reset pins.
Once programmed, it acts just like a regular 555, except with a very long delay.


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