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Radionova 1 Frequency Synthesizer

Radionova 1 Frequency Synthesizer

Reference Oscillator



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Above — Reference oscillator schematic. A low noise 2 MHz signal gets digitized by a BJT switch offering the correct voltage swing to properly clock an intriguing CMOS level circuit I learned about from Wes. The 74HC193 and 74HC74 4-bit ripple counter + D flip flop perform the division where R = 3 to 17. Each R gets chosen by flipping 4 front-panel mounted toggle switches.

Wes once shared that the divider scheme idea essentially came from the 74HC193 data sheet where they show what happens when its plied as a down counter ( where you load a number and then count down until it reaches 0 ). That number gets augmented by 2.  1 comes from the HC7474 D-FF that follows the 74HC193, while the other comes from the phasing of the signals. The HC7474 makes the overall output coherent with the clock and eliminates the flicker noise that might be generated by the longer divider chain inside the 74HC193. 

In this PLL synthesizer, the VCO does not get divided, so N = 1 thus it avoids the usual 20 log N phase noise addition when the reference frequency is multiplied up to get the VCO frequency.

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Above — ‘Scope capture of the low distortion, reference oscillator output. Inside the feedback loop, reference oscillator noise dominates, so a quiet reference makes sense.

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Above — ‘Scope capture of the reference oscillator transistor switch output now at CMOS drive level to clock the reference oscillator divider circuitry. 


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Above — Table of all possible switch settings, the division integer R, the resultant VCO frequency and 
the varactor tuning DC voltage as measured on the output of the VCO filter on the PLL board. That’s the DC voltage that changes the VCO frequency within the loop. To lower noise, it’s important to keep a couple of volts DC or so on the VCO varactors at your lowest frequency. Further, I noticed if the varactor tuning voltage drops below ~ 0.4 VDC, the loop may suffer instability.

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Above — Scope captures of the reference oscillator set at the lowest and highest division settings. You just add the reference divider frequency to 20 MHz to get the VCO output frequency.

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Above — Reference oscillator breadboard prototype