The PCI Express® is primarily intended as a high-performance serial interface targeted for use in desktop, mobile, workstation, server, communications platforms, and embedded devices. As with any modern high-speed serial design, the performance of an actual PCI Express® interconnect is highly dependent on the implementation. Recent advances in technology have allowed PCI Express® designs to reliably reach 8.0 GT/s using common PCB materials and advanced Tx and Rx equalization techniques. This paper describes a statistical simulation compliance method applied to proven Samtec designs. This application note is intended to help engineers deploy systems of two PCB cards connected through Samtec’s family of high-speed PCI Express® Jumper 85 ohm cable assemblies.
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To demonstrate the feasibility of using Samtec’s PCIEC PCI Express® 85 ohm Jumper cable assembly mated with a PCIE high speed socket with standard FR4 epoxy PCBs, statistical simulations will be used to characterize the full Tx die-to- Rx die PCIE 8.0 GT/s channel, utilizing Samtec Final InchTM s-parameter modeling of the connector and complete interconnect channel, including all aggressor crosstalk impacts.
