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Working with the Xilinx Virtex-E FPGA in a huge BGA package

Working with the Xilinx Virtex-E FPGA in a huge BGA package

Bill of materials

I’m not expecting anyone to actually want to build this as a complete development board but just in case, here’s the full bill of materials.

Identifiers Value Quantity Description Footprint
C1, C2, C3, C4, C5, C6, C7, C53, C54, C55, C56, C57 2.2µ 12 Ceramic capacitor 0402
C8, C14, C15, C16, C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C45, C46, C47, C48, C49, C50, C51, C52 470n 22 Ceramic capacitor 0402
C9, C10, C11, C12, C13, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, C37, C38, C39, C40, C41, C42, C43, C44, C58, C59, C60, C61, C62, C63, C64, C65, C66, C67, C68, C69, C70, C71, C72 47n 38 Ceramic capacitor 0402
C73 15p 5% 1 Ceramic capacitor 0603
C74, C81, C82, C83, C84 22µ 5 Ceramic capacitor 0805
C75 470n 1 Ceramic capacitor 0603
C76, C78 10µ 2 Ceramic capacitor 0805
C77 8200p 1 Ceramic capacitor 0603
C79, C80, C85, C86, C87, C88 100n 6 Ceramic capacitor 0603
C89, C90 470µ 2 Electrolytic capacitor Radial 4x8x12mm
D1 Schottky 1 ST Micro STPS3L40S DO-214AB
D2 red LED 1 Power LED 0603
D3, D4, D5, D6, D7 red LED 5 Indicator LEDs 2012
L1, L2 3.3µ 2 LQH44PN3R3MP0L 4x4mm
P1 GPIO Header 39×3 1 39×3 pin header 2.54mm
P2 GPIO Header 28×2 1 28×2 pin header 2.54mm
P3 USB mini B 1 USB power entry SMD
P4 Header 1×4 1 1.8V power header 2.54mm
P5 Header 1×2 1 GCK2 input 2.54mm
P6 Header 1×2 1 50MHz oscillator enable 2.54mm
P7 Header 2×6 1 CLK/MODE header 2.54mm
P8 Header 1×5 1 PROG header 2.54mm
P9 Header 2×7 1 JTAG IDC boxed header 2.54mm
P10 Header 2×2 1 3.3V power header 2.54mm
P11 Header 1×4 1 5V power header 2.54mm
R1 27k 1% 1 SMD resistor 0603
R2 100k 1 0603
R3 20k 1% 1 0603
R4 45.3k 1 0603
R5, R7, R8, R9, R10, R11, R12, R13 10k 8 0603
R6, R14, R15, R16, R17, R18 390 6 0805
R19, R20, R22, R23, R24, R25, R26, R27, R30, R31, R32, R33, R34, R37, R38, R39, R40, R41, R42, R43 100 20 0402
R21, R28, R29, R35, R36 187 5 0402
SW1 Button 1 PCB mount button through hole
U1 XCV600e FPGA 1 Xilinx Virtex-e FG676 BGA
U2 LMR10515 1 TI switching regulator SOT23-5
U3 TPS54339DDA 1 TI switching regulator SO-8 powerpad
U4 S25FL127S 1 Spansion 128Mb flash SO-8 (208mil)
U5 MT48LC16M16A2P-6A 1 Micron SDRAM TSOP2-54
U6 IS61LV5128AL 1 ISSI 512Kb SRAM TSOP2-44
X1 ASE-50.000MHZ-LR-T 1 Abracon 50MHz oscillator 3.2×2.5mm



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PCB Design and Layout

I stated earlier that I would be constraining the board size to 10x10cm so that I can qualify for an affordable prototype four layer service. The next decision to make is the layer stackup.

I went for a commonly used arrangement of signal – ground – power/signal – signal. Having a ground plane directly below the top means that I can do impedance controlled routing on the top layer with traces that don’t have to be very wide. All the differential pairs are set to the correct 12.3 mil width for 50Ω impedance control on this board.

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