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Working with the Xilinx Virtex-E FPGA in a huge BGA package

Working with the Xilinx Virtex-E FPGA in a huge BGA package

GPIO bank

I’ve exposed 78 GPIOs here which ought to be enough to keep me happy for the forseeable future. You can’t see it in the diagram but this row of GPIOs is arranged as a 39×3 block with the column running down the middle connected to GND. This arrangement allows me to connect a 2-row IDC ribbon cable directly to the GPIO block and have every other pin being GND. This is a common arrangement used to maintain signal integrity in a single-ended parallel cable. See the layout of the wires on a JTAG cable for a good example of this in practice.

Differential pairs



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I’ve chosen to expose as many of the FPGA’s differential pairs as I can route out and these can of course be used for normal single-ended signals as well. Unfortunately these old FPGAs don’t support on-chip dynamic impedence matching so you should terminate the differential pairs on the PCB. Xilinx recommends serial termination for receivers and series-parallel termination for transmitters. I’ve included roughly equal numbers of pairs terminated as transmitters and receivers on this board.

Static RAM

I said in the introduction that I was going with a theme of external memory interfaces on this board and I’ve got started here with a 512kb chunk of SRAM, the IS61LV5128AL 8-bit 10ns part from ISSI. I know this part well from my previous FPGA graphics accelerator project so driving it here won’t be a problem.

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