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Working with the Xilinx Virtex-E FPGA in a huge BGA package

Working with the Xilinx Virtex-E FPGA in a huge BGA package

Development board schematic

Here’s the full schematic and it’s a big one. Click on the thumbnail to download a PDF.

Let’s take a look at each section of the schematic in more detail.

The FPGA banks

The XCV600E is so big that it’s split up into logical sections on the schematic. Most obvious are each of the banks of logic. Inside an FPGA the fabric is divided into separate banks of related logic, each with its own power supply and voltage reference inputs and all the banks are interconnected by high speed routing logic and low-skew clock distribution nets.

Missing from these older FPGAs are hard logic blocks such as multipliers, DSP functionality and differential serialisers. If you need those then you have to create them out of the fabric. Newer FPGAs tend to feature all of these and more which makes it easier to get a new design off the ground with some basic building blocks created from hard logic.



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The diagram from the datasheet also shows where the global clocks (GCLKs) enter into the device. It’s expected that the global clocks will be high-fanout nets — that is, pretty much every one of your HDL processes will receive a signal from a GCLK or some derivation of it. Therefore these nets are designed to reach all banks in the device with very low skew. Clock skew in an FPGA can lead to metastability bugs which must rank amongst the hardest class of bugs to find.

I’ve selected I/Os to expose on the development board based on several factors. All I/Os with an alternate function are exposed such as JTAG and other programming methods as well as all the clocks. As many differential pairs as I can are exposed along with as many GPIO I/Os as I can route on the four layer board.

Clocks

There are four GCLKs on the XCV600E and all of them can be either single ended or differential. I’ve exposed GCLK0, 1 and 2 as pin headers and provided 100Ω parallel termination for the differential pairs. GCLK3 is connected to a 50MHz on-board oscillator that provides a single-ended CMOS 50MHz signal on the positive GCLK3 I/O. This signal can be disabled by removing the jumper on P6.

The Virtex-E has eight on-board delay locked loops (DLLs). These allow a GCLK to be doubled or divided by 1.5, 2, 2.5, 3, 4, 5, 8, or 16.

In addition to that, one DLL can be linked to another to yield a 4x multipler. It was with this in mind that I selected the 50MHz on board clock. With the doubling, linking and all those dividers I can reach a lot of useful frequencies. These DLLs are not as powerful as the Digital Clock Manager (DCM) in the Spartan FPGAs but there are a lot of them on board and the combination of doublers, dividers and chaining allow good flexibility.

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