8. Design Rules Checking (DRC)

Design Rules Checking (DRC) is a powerful automated feature than is available in most PCB design software that checks the design against any or all of the design rules set during the constraint definition stage.  Running the DRC results in the generation of a report which is used as reference to clear the violations of the constraints.

Shown above is the DRC window in Altium Designer. Click on image for a larger view.

9. Gerber file generation

Once all errors listed in the DRC report are corrected and other review comments are updated in the PCB design, the designer can move towards generating Gerber file for PCB fabrication.  Gerber format is a standard format used by the electronics industry for communicating the PCB design information to fabrication.  It is an open ASCII vector format for 2D binary images.  The set of documents for fabrication consists of a gerber file for each image layer of the PCB design.  A standard set of files consist of a gerber file for :

1. Copper layers
2. Solder mask
3. Silkscreen/Legend

Additionally an NC drill file is also created which is an input program to a numerically controlled drilling machine for automated drilling of the Printed Circuit board.

Other formats for fabrication are IPC-D-350C and ODB++. Additional information to be provided to the PCB manufacturer is listed below :

1. A board name/number and a revision number
2. Number of boards required
3. Thickness of the board. 1.6mm is commonly used.
4. Number of layers
5. Surface finish (HASL, OSP, ENIG). HASL is commonly used.
6. Color of solder mask and silkscreen
7. Minimum track thickness and clearance
8. Weight of copper (1.0 oz is standard)
9. Bare board testing (BBT) requirement

Very often a PCB designer is required to satisfy both international and domestic regulations and standards.  Hence it is critical for a PCB designer to be aware of the best practices in PCB design for EMC compliance.

10. PCB design for EMC compliance – Best practices

1. Use surface mount components as far as possible due to reduced inductances and closer placements possible and hence reducing the lengths of the traces
2. Signal returns paths take the shortest possible course on the ground plane. Make sure that there are no discontinuities in the ground plane.  When the return paths of the signal are long, it creates a ground loop which acts like an antenna and radiates emissions.
3. Use ferrite beads to filter signals entering the board from external source. The ferrite bead should be placed as close as possible to the entry point.
4. Isolate noisy traces from other traces so that they do not pick up the noise
5. When the length of the trace is such that the time taken for propagation from source to destination is greater than the rise/fall times of the signal, the trace is considered as a transmission line and series termination is to be added to the trace to prevent reflection.
6. Do not place clock circuits near the edge of the board or near I/O connectors. Clock traces and other high speed traces should ideally be routed as short as possible and adjacent to a ground plane which keeps emissions and cross talk under control.  If the board density is high and it is not possible to provide sufficient isolation from other traces, it is imperative to provide ground guard traces on both sides of the high speed traces in order to avoid crosstalk.
7. Analog signal trace should be isolated from clock and other high speed switching signals so that the high frequency noise is not coupled on to the analog signals which would prove to be a disaster
8. Decoupling/bypass capacitors are used to filter the high frequency noise in the power lines. Use ample number of decoupling capacitors and make sure that they are placed very close to the power pins.
9. Minimize layer changing vias when routing a track. Via introduce undesirable inductance in the traces.

UP NEXT:

PCB Thermal managemet, Single layer PCB design and Conclusion