Altera PHYLite for Parallel Interfaces Loopback
This application note showcases loopback reference designs using the Altera PHYLite IP core.
This document is divided into three segments:
- A simple input/output PHYLite simulation reference design.
- A simple input/output PHYLite with dynamic reconfiguration using Arria 10 devices hardware reference design.
- Functional description for the modules and application used in both reference designs.
The simulation reference design is a simple design that simulates the behavior of the Altera PHYLite IP core. This design consists of 2 main components:
- A device Under Test (DUT) module that includes two Altera PHYLite IP instances.
- A traffic generator module