An experiment to observe the sense output whilst flipping the state of a single bit in an early Univac III magnetic core memory plane.
Organised as 64 rows by 64 columns, this Univac III core memory plane of early 60’s vintage has a storage capacity of 4096 bits. I bought it on eBay, not with the intention of having it framed, but to make some sort of retro-computing demonstrator, possibly using discrete transistors. I don’t know how far I’ll get with this, but I’ve taken the first step by reading and writing a single bit.
I had no specific information about the plane to start with. My aim was to experimentally determine: half select current; sense pulse amplitude and position. The next step is to design a sense amplifier with a strobe to sample at the point of maximum signal-to-noise.
The sleeved wires at the top of the photo, terminated to the left and right of the (modern) green edge connector, are the inhibit wire. This can clearly be seen running parallel to the vertical select wires in Zoom3. The green crocodile clips are attached to the sense wire.
To produce a steady trace on the ‘scope, the test circuit flips a core continuously. A write is followed by two reads. The logical “1” written is flipped to “0” by the first destructive read. The read/write sequence is controlled by a 16V8 GAL, but no such devices will be permitted in my retro-computing demonstrator!
The output of constant current source Q1 is fed through the XY select wires by H-bridge Q2, 3, 7, 8. Trimmer VR1 sets the half select current. Typically, this varies between 150 and 500mA, depending on core size. Around 400mA seems to be about right for this plane, which has quite large cores. Conveniently, since I’m only flipping one core, the X and Y select wires are driven in series.
The driver was simulated in LTSpice to estimate rise-time. This was another unknown: too slow and I’d get a weak sense pulse; too fast and there’d be excessive ringing. The prediction was 100ns, but I had no idea if that was OK. According to James R Jones’ excellent article [1,2] it “should be about half the core design time for a 1 peak to occur” which turned out to be 400ns, so I was a bit fast.
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