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Working with the Xilinx Virtex-E FPGA in a huge BGA package

Working with the Xilinx Virtex-E FPGA in a huge BGA package
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Escape routing

The first issue is escape routing the balls. Escape routing is the process of routing out traces from between the balls to the PCB at large. The size of the traces and vias that you can use depends on the pitch of the ball grid. Thankfully Xilinx publish XAPP157 which explains the recommended design parameters for complete escape routing of the FG676 package.

The only problem with the design rules in that table is the requirement for six layers. The cheap Chinese prototyping houses cannot yet do six layer boards at a hobby-friendly price. You’re looking at a few hundred pounds for a pack of ten compared to about fifty pounds for a four layer pack. I’ll just have to work with four layers and not route out all the pads. The chances are that I won’t have board space to route them all out anyway.


Further in the document Xilinx even give a suggested escape routing strategy for each layer.

The two missing layers from the diagram are the solid ground and split power planes. Even though I’m not going with a six layer design I’ll still use this as a guide for establishing patterns used to route out adjacent balls.


Another advantage of these older BGA packages is that they’re not lead-free. If you’re looking at a Xilinx BGA device code then the ‘FG’ part of the name means leaded and ‘FGG’ would mean ‘lead free’. Leaded balls melt at an appreciably lower temperature than lead-free which means that I stand a better chance of success in my reflow oven because higher temperatures mean that the risk of damage to components increases.

I’ve managed to convince myself that I can deal with this package and create a development board for it so it’s time to come up with a schematic.

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