The family of ADC32RFx5 is a dual-channel 14-bit analog to digital converter (ADC) and provides 3 Gsps of ADC sample rate. This device has a total of 8 lane JESD204B interfaces, 4-lane per ADC, with a maximum input bit rate of 12.3 Gbps. ADC32RFx5 supports JESD204B subclass 1 for multi-chip synchronization by using SYSREF. Up to 32 of decimation function enables system designers to receive minimum 93.75 Msps of baseband rate to FPGA, and four independent Numerically Controlled Oscillator (NCO) supports 4 different frequency bands from one ADC32RFx5 device.
Each of ADC channels is internally connected two dual band digital down converters (DDC) and independent 16-bit numerically controlled oscillator (NCO). The DDC block in ADC32RFx5 can also be bypassed to achieve the maximum Nyquist bandwidth, which supports more than 1GHz of IBW for the next generation (5G) cellular system.
The ADC32RFx5 provides on-chip DDC block that can be controlled with serial-to-parallel interface (SPI) register settings and the GPIO pins. The DDC block supports 2 basic operating modes – receiver (RX) with single or dual band DDC or wide bandwidth observation receiver. Each of ADC channels is followed by two DDC chains consisting of the decimation filter along with 16-bit NCO, and the output to FPGA can be real or complex format.
In this document, 800MHz (40xLTE20MHz) of IBW from DAC38RF8xEVM is fed into the input of ADC32RFx5EVM. The application report RF Sampling DAC with 800 MHz of LTE IBW (SLAA709) describes the profile of test pattern, operation of DAC38RF8x and evaluated performance from the board