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82571EB/82572EI Gigabit Ethernet Controller Design Guide

82571EB/82572EI Gigabit Ethernet Controller Design Guide

The Intel® 82571/82572 Gigabit Ethernet Controller is a single, compact component that offers either one (82572) or two (82571) fully integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) ports. This device uses the PCI Express* (PCIe) architecture (Rev. 1.0a).

The Intel 82571/82572 Gigabit Ethernet Controller enables single- or dual-port Gigabit Ethernet implementation in a very small area and can be used for server and workstation network designs with critical space constraints. The Intel 82571/82572 Gigabit Ethernet Controller provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). Each port also contains a Serializer-Deserializer (SERDES) to support 1000Base-SX/LX (optical fiber) and Gigabit backplane applications. In addition to managing MAC and PHY Ethernet layer functions, the controller manages PCI Express packet traffic across its transaction, link, and physical/logical layers.



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The Intel 82571/82572 Gigabit Ethernet Controller’s on-board System Management Bus (SMB) ports enable network manageability implementations required by information technology personnel for remote control and alerting via the LAN. With SMB, management packets can be routed to or from a management processor. The SMB ports enable industry standards, such as Intelligent Platform Management Interface (IPMI) and Alert Standard Forum (ASF) 2.0, to be implemented using the 82571/82572 Gigabit Ethernet Controller. In addition, on-chip ASF 2.0 circuitry provides alerting and remote control capabilities with standardized interfaces. The 82571EB/82572EI controller contains a dedicated microcontroller for manageability.

The 82571/82572 Gigabit Ethernet Controller with PCIe architecture is designed for high-performance and low-host-memory access latency. The device connects directly to a system Memory Control Hub (MCH) using either one or four PCIe Lanes.

Wide internal data paths eliminate performance bottlenecks by efficiently handling large address and data words. Combining a parallel and pipelined logic architecture optimized for gigabit ethernet and independent transmit and receive queues, the 82571/82572 Gigabit Ethernet Controller efficiently handles packets with minimum latency. The 82571/82572 Gigabit Ethernet Controller includes advanced interrupt handling features. The 82571/82572 Gigabit Ethernet Controller uses efficient ring buffer descriptor data structures, with up to 64 packet descriptors cached on chip. A large 48 KByte on-chip packet buffer maintains superior performance. In addition, using hardware acceleration, the controller offloads tasks from the host, such as TCP/ UDP/IP checksum calculations and TCP segmentation.

 




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