This article reverse-engineers the flag circuits in the ARM1 processor, explaining in detail
how the flags are generate, controlled, and used.
Condition flags are a key part of most computers, since they allow the computer to change what it does based on various conditions.
The flags keep track of conditions such as a value being negative or zero or an overflow happening.
Processors may also have status flags to control modes such as running in user mode versus
protected (kernel) execution.
The ARM1 processor stores these flags in a special register called the Processor Status Register (PSR).
The ARM1 chip is interesting to examine not only because it is simple enough to understand but also because it was the first ARM processor. There are now tens of billions of ARM processors in use, probably powering your smartphone right now.
This article is part of my series on reverse-engineering the ARM1.
Processor flags seem like they should be trivial, but there’s a lot more involved than you might expect.
You might want to start with my first article for an overview of the chip.
The die photo below shows the ARM1 chip. This article concentrates on the flag logic, highlighted in red. As you can see, flags take up a significant part of the chip.
The flags interact with many other parts of the chip:
the trap control logic handles interrupts and exceptions;
the register control logic handles access to the chip’s registers including the program counter (PC); when the Arithmetic-Logic Unit (ALU) performs computations it stores status in the flags;
the Barrel Shifter shifts or rotates values, sending shifted bits to the flags;
and the Instruction Register holds instructions as they are read from memory and feeds them to the decode logic to be interpreted.
In the upper left, the M0 and M1 pins indicate the mode bits stored in the flags.
The article will describe how all these components interact with the flags.