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The ARM1 processor’s flags, reverse engineered

The ARM1 processor’s flags, reverse engineered
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Some ARM1 background

This section summarizes a few features of the ARM1 processor that are important for understanding the flags.
The ARM1 is a 32-bit processor with 16 32-bit registers called R0 through R15 (and some extra registers that will be described later).
The processor has a 26-bit address space.

One unusual feature of the ARM1 processor is it combines the flag bits in the processor status register (PSR) and the program counter (PC) into a single register, R15, the PC/PSR. Because of the 26-bit address space, the top 6 bits of the 32-bit PC register are unused. In addition, instructions are always aligned on a 32-bit boundary, so the bottom two PC bits are always 0. These eight unused PC bits were instead used for flags, as shown in the diagram below.

 

The Processor Status Register in the ARM1 processor is combined with the program counter.

The Processor Status Register in the ARM1 processor is combined with the program counter. From page 2-26 of the ARM databook.

Four condition flags hold the status of arithmetic operations or comparisons.
The negative (N) flag indicates a negative result.
The zero (Z) flag indicates a zero result.
The carry (C) flag indicates a carry from an unsigned value that doesn’t fit in 32 bits.
The overflow (V) flag indicates an overflow from a signed value that doesn’t fit in 32 bits.
The next two bits are used to enable or disable interrupts: the I flag controls regular interrupts, while the F flag controls the chip’s special fast interrupts.
The bottom two bits (M1 and M0) control the processor’s execution mode:
user, supervisor (kernel), interrupt handler, or fast interrupt handler.
These modes will be discussed in more detail later.

Two instruction classes that are important to flags are the data processing instructions and the block data transfer instructions.
Since the ARM has a simple,
orthogonal instruction set,
these operations can operate on the R15 with the flags as easily as any of the other registers.



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The data processing instructions are the arithmetic-logic instructions.
There are 16 types of data processing operations, such as addition, subtraction, Boolean operations such as AND, and comparison.
Unlike most processors, the ARM makes updates of the condition flags optional. The instruction includes a bit called the “S” bit. If the S bit is set, the instruction updates the condition flags; otherwise the flags remain unchanged.
The data processing instructions can also act on R15 directly, causing the flags to be read or modified.

The ARM also provides block data transfer instructions: LDM (load multiple) and STM (store multiple). These instructions load a selected set of registers from memory or store them to memory,
for example popping registers from the stack or pushing them to the stack.
These instructions can also use R15, accessing or modifying the flags.

Floorplan of the ARM1 chip, from ARM Evaluation System manual. (Bus labels are corrected from original.)

Floorplan of the ARM1 chip, from ARM Evaluation System manual. (Bus labels are corrected from original.)

While the program counter (PC) and flags are architecturally part of the same register R15, they are physically separated on the chip, as you can see from the die photo and the floorplan diagram above.
The flags are labeled PSR, above the ALU, while the PC is on the left of the register file.
Interestingly, the original sketch for the ARM1 (below) show the PSR flags right next to the PC.
While the final chip architecture largely matched the sketch, some components moved. In particular, several functional units were moved to the top of the chip, above the instruction bus (orange).

Original sketch of the ARM1 chip layout. Note the Processor Status Register (PSR) is on the left; the final chip put it above the ALU. Photo courtesy of Ed Spittles.

Original sketch of the ARM1 chip layout. Note the Processor Status Register (PSR) is on the left; the final chip put it above the ALU. Photo courtesy of Ed Spittles.
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